Issue 01 · September 2026About  ·  RSS

SILICON5 min read

Two nanometres, sold out until 2028

TSMC's newest node is booked through 2028 and ten of its fifteen announced customers are building for the datacentre. The scarcest thing in the supply chain is no longer the lithography.

TSMC's N2 process entered volume production in the fourth quarter of 2025 and accounted for about three per cent of wafer revenue by the second quarter of 2026 — a small share that understates what is happening, because the capacity is spoken for. The node is reported booked through 2028, and the company is pushing toward roughly 100,000 wafer starts a month by the end of this year, with further expansion of both N2 and N3 planned into next.

TSMC 2 nm customers by segment 10 of 15 customers are designing high-performance compute HPC Everything else ANNOUNCED N2 CUSTOMERS, ONE DOT EACH
The customer mix has flipped. Leading nodes used to be claimed first by phones. On N2, high-performance compute took two thirds of the announced slots.

Who is buying

Of the fifteen customers announced for N2, around ten are high-performance compute designs. That is a reversal of the historical pattern, in which smartphone silicon claimed the leading node first and datacentre parts followed a generation behind, because phone volumes justified the risk and the price.

The price is now roughly thirty thousand dollars a wafer. At that number the economics only close for products with very high value per square millimetre, and the accelerator business is more or less the only one that qualifies at volume. The consequence is that the most advanced manufacturing capability on Earth has been redirected, in a single generation, from consumer devices to machine learning infrastructure.

The bottleneck moved

It is worth being precise about where the constraint actually sits. For most of the past three years the limiting factor on AI accelerator shipments has not been transistor fabrication but advanced packaging — specifically CoWoS, the chip-on-wafer-on-substrate technique that bonds logic dies to stacks of high-bandwidth memory on a silicon interposer. A leading-edge compute die is useless without the memory bandwidth beside it, and that assembly step has its own capacity, its own yield learning curve and its own long equipment lead times.

TSMC is expanding CoWoS at its Advanced Backend Fab 7 in Chiayi. The relevant question for anyone forecasting accelerator supply is not how many N2 wafers exist but how many finished packages the back end can produce — a number that has repeatedly turned out to be the binding one.

What a sold-out node means

Full booking through 2028 is usually reported as strength, and for the manufacturer it is. For everyone downstream it is a description of inflexibility. A start-up with a genuinely better architecture cannot buy its way onto the leading node on a useful timescale; allocation is settled years ahead among parties large enough to prepay. And if AI capital expenditure turns, the capacity cannot be repointed at consumer products quickly, because those products were designed for the nodes they could afford.

Concentration of this kind is not new to semiconductors. What is new is that the concentration is now inside one demand category, at one company, in one packaging technology, at one back-end site.


Elsewhere in Issue 01

September 2026

PHYSICS7 min

One flash, a mile under South Dakota

The LZ experiment has recorded a nuclear recoil that no known background explains. At 2.6 sigma it is not a discovery. It is something rarer: a clean anomaly in the most carefully swept room on Earth, and the collaboration has chosen to show its working in public.

ENERGY6 min

The magnets are in. Now comes the plasma.

SPARC is about 80 per cent assembled and aiming at first plasma in 2027. The bet it represents is narrower, and more testable, than the word fusion suggests.